Data storage control apparatus and data storage control method

ABSTRACT

A compressed data generator compresses, by using a lossless compressor and a lossy compressor, image data in units of first blocks to generate a plurality of types of compressed data. A selector performs selection processing in units of second blocks each including a predetermined number N of first blocks, where N is an integer of 1 or more. The selection processing involves determining whether each of the plurality of types of compressed data satisfies a selection condition and selecting one piece of compressed data that satisfies the selection condition. The selection condition includes a data size condition that a data size of all the first blocks included in the second block is less than or equal to a predetermined value, and a data accuracy condition that information maintaining accuracy is highest among compressed data that satisfy the data size condition.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data storage control apparatus and adata storage control method.

2. Description of the Background Art

Various techniques are related to data storage.

For example, image data of still images and moving images is compressedto reduce the amount of data. Japanese Patent Application Laid-Open No.2009-260977 describes a technique for compressing video data to asmaller size, using a combination of irreversible compression andreversible compression. Japanese Patent Application Laid-Open No.2013-135254 describes a technique that is highly likely to be able toreduce the amount of data while generating lossless data without datadegradation.

Japanese Patent Gazette No. 5147102 describes a technique for accessingmemory that includes a plurality of banks and that requires an intervalequal to or longer than a predetermined number of clock cycles betweentwo successive accesses that are made to the same bank.

Various demands are made of data storage technology. Examples includedemands for a reduced amount of memory capacity that is used and forefficient use of memory. The techniques of the above-described threedocuments (Japanese Patent Application Laid-Open Nos. 2009-260977 and2013-135254 and Japanese Patent Gazette No. 5147102) are consideredexamples of techniques that have been developed to meet the abovedemands.

SUMMARY OF THE INVENTION

It is an object of the present invention to achieve either a reductionin the use amount of memory capacity or efficient use of memory, forexample, with a technique that is completely different from conventionaltechniques.

A data storage control apparatus according to a first aspect of thepresent invention includes a compressor that compresses image data andoutputs compressed data, and a writing controller that writes thecompressed data as write data to a memory. The compressor includes acompressed data generator that includes a lossless compressor forperforming lossless compression and a lossy compressor for performinglossy compression, and that compresses, by using the lossless compressorand the lossy compressor, the image data in units of first blocks, eachbeing an image block of a predetermined area size, to generate aplurality of types of compressed data in parallel or in series, and aselector that performs selection processing on each second block thatincludes a predetermined number N of the first blocks, where N is aninteger of 1 or more, the selection processing involving determiningwhether each of the plurality of types of compressed data generated bythe compressed data generator satisfies a predetermined selectioncondition and selecting one piece of compressed data that satisfies thepredetermined selection condition. The predetermined selection conditionincludes a data size condition that a data size of all of the firstblocks included in the second block is less than or equal to apredetermined value, and a data accuracy condition that informationmaintaining accuracy is highest among the compressed data that satisfiesthe data size condition. The writing controller writes the one piece ofcompressed data selected by the selector as the write data to thememory.

A data storage control apparatus according to a second aspect of thepresent invention is the data storage control apparatus of the firstaspect in which the lossless compression is processing for obtaining adifference in pixel value between a compression target pixel and astandard pixel and assigning a resultant difference value to thecompression target pixel, and the lossless compressor defines thecompression target pixel and the standard pixel in the first block inaccordance with a predetermined pixel classification and performs thelossless compression on the compression target pixel and the standardpixel that have been defined.

A data storage control apparatus according to a third aspect of thepresent invention is the data storage control apparatus of the secondaspect in which the predetermined pixel classification includes a firstpixel classification according to which pairs of pixels are sequentiallyselected in the first block, each of pairs including pixels adjacent toeach other in the first block that are defined with one pixel as thecompression target pixel and the other pixel as the standard pixel.

A data storage control apparatus according to a fourth aspect of thepresent invention is the data storage control apparatus of either thesecond or third aspect in which the predetermined pixel classificationincludes a second pixel classification according to which a pixel at apredetermined fixed position in the first block is defined as thestandard pixel, and each pixel at a position other than the fixedposition in the first block is defined as the compression target pixel.

A data storage control apparatus according to a fifth aspect of thepresent invention is the data storage control apparatus of one of thefirst to fourth aspects in which the lossy compressor includes aplurality of lossy compression processors that perform different typesof lossy compression.

A data storage control apparatus according to a sixth aspect of thepresent invention is the data storage control apparatus of one of thesecond to fourth aspects in which the lossy compressor includes at leastone of a first lossy compression processor that generates firstcompressed data by performing first low-pass processing using a firstlow-pass filter on compression target data, a second lossy compressionprocessor that generates second compressed data by performing the firstlow-pass processing and the lossless compression in this order on thecompression target data, and a third lossy compression processor thatgenerates at least one piece of third compressed data by performing thefirst low-pass processing and the lossless compression in this order onthe compression target data and performing a first bit shift processingin which a bit of the difference value obtained from the losslesscompression is shifted toward the least significant bit.

A data storage control apparatus according to a seventh aspect of thepresent invention is the data storage control apparatus of the sixthaspect in which the at least one piece of third compressed data is aplurality of pieces of third compressed data that are generated by usingdifferent shift amounts in the first bit shift processing.

A data storage control apparatus according to an eighth aspect of thepresent invention is the data storage control apparatus of the sixth orseventh aspect in which the lossless compression performed by at leastone of the second lossy compression processor and the third lossycompression processor uses a compression technique different from atechnique used in the lossless compression performed by the losslesscompressor.

A data storage control apparatus according to a ninth aspect of thepresent invention is the data storage control apparatus of one of thesixth to eighth aspects in which the lossy compressor further includesat least one of a fourth lossy compression processor that generatesfourth compressed data by performing second low-pass processing using asecond low-pass filter on the compression target data, the secondlow-pass filter having a different strength from the first low-passfilter, a fifth lossy compression processor that generates fifthcompressed data by sequentially performing the second low-passprocessing and the lossless compression on the compression target data,and a sixth lossy compression processor that generates at least onepiece of sixth compressed data by performing the second low-passprocessing and the lossless compression in this order on the compressiontarget data and performing a second bit shift processing in which a bitof the difference value obtained from the lossless compression isshifted toward the least significant bit.

A data storage control apparatus according to a tenth aspect of thepresent invention is the data storage control apparatus of the ninthaspect in which the at least one piece of sixth compressed data is aplurality of pieces of sixth compressed data that are generated by usingdifferent shift amounts in the second bit shift processing.

A data storage control apparatus according to an eleventh aspect of thepresent invention is the data storage control apparatus of either theninth or tenth aspect in which the lossless compression performed by atleast one of the fifth lossy compression processor and the sixth lossycompression processor uses a compression technique different from atechnique used in the lossless compression performed by the losslesscompressor.

A data storage control apparatus according to a twelfth aspect of thepresent invention is the data storage control apparatus of one of thefirst to eleventh aspects in which the lossy compressor includes aseventh lossy compression processor that generates seventh compresseddata by performing bit-reduction processing on a compression targetpixel in compression target data, the bit-reduction processing involvesdeleting a predetermined range of bits from the least significant bitside of a bit string that represents the pixel value to reduce thenumber of bits of the pixel value, and the predetermined range is setsuch that the seventh compressed data always satisfies the data sizecondition.

A data storage control apparatus according to a thirteenth aspect of thepresent invention is the data storage control apparatus of one of thefirst to twelfth aspects in which the lossless compressor and the lossycompressor operate in parallel.

A data storage control apparatus according to a fourteenth aspect of thepresent invention is the data storage control apparatus of one of thefirst to thirteenth aspects that further includes an input buffer memorythat temporarily stores the image data that is to be supplied to thecompressor. The lossless compression or the lossy compression includesreference-type processing that uses, as a reference object, a firstblock that is not set to a compression object among the first blocks,and the input buffer memory stores the image data of a first block thatis scheduled to be used as either the compression object or thereference object, and frees a storage area allocated to a first blockthat is no longer scheduled to be used as either the compression objector the reference object, at a predetermined timing.

A data storage control apparatus according to a fifteenth aspect of thepresent invention is the data storage control apparatus of thefourteenth aspect in which the compressor acquires the image data inunits of third blocks, each including a predetermined number X of thesecond blocks, where X is an integer of 1 or more, from the input buffermemory, and the input buffer memory manages the storage area inassociation with the third blocks.

A data storage control apparatus according to a sixteenth aspect of thepresent invention is the data storage control apparatus of either thefourteenth or fifteenth aspect that further includes an output buffermemory that temporarily stores the write data that is output from thecompressor for the supply to the writing controller. The memory includesa plurality of banks, and the writing controller writes the write datato the memory while switching the plurality of banks every piece of thewrite data.

A data storage control apparatus according to a seventeenth aspect ofthe present invention is the data storage control apparatus of thesixteenth aspect in which the writing controller waits for Y banks'worth of the write data to be accumulated in the output buffer memory,where Y is an integer of 2 or more, and collectively writes the Y banks'worth of the write data to the memory.

A data storage control apparatus according to an eighteenth aspect ofthe present invention is the data storage control apparatus of one ofthe fourteenth to seventeenth aspects in which upstream of the inputbuffer memory, image processing is performed in units of microblocks,and a predetermined number V of the second blocks corresponds to apredetermined number W of the microblocks, where V and W are integers of1 or more.

A data storage control method according to a nineteenth aspect of thepresent invention includes (a) compressing image data and outputtingcompressed data, and (b) writing the compressed data as write data in amemory. The step (a) includes (a−1) compressing, by using losslesscompression and lossy compression, the image data in units of firstblocks, each being an image block of a predetermined area size, togenerate a plurality of types of compressed data in parallel or inseries, and (a-2) performing selection processing on each second blockthat includes a predetermined number N of the first blocks, where N isan integer of 1 or more, the selection processing involving determiningwhether each of the plurality of types of compressed data generated inthe step (a−1) satisfies a predetermined selection condition, andselecting one piece of compressed data that satisfies the predeterminedselection condition. The predetermined selection condition includes adata size condition that a data size of all of the first blocks includedin the second block is less than or equal to a predetermined value, anda data accuracy condition that information maintaining accuracy ishighest among the compressed data that satisfies the data sizecondition. In the step (b), the one piece of compressed data selected inthe step (a-2) is written as the write data in the memory.

A data storage control apparatus according to a twentieth aspect of thepresent invention includes a compressor that compresses image data andoutputs compressed data, a writing controller that writes the compresseddata as write data in a memory, and an input buffer memory thattemporarily stores the image data that is to be supplied to thecompressor. The compressor compresses the image data in units of firstblocks, each being an image block of a predetermined area size, andoutputs the compressed data in units of second blocks, each including apredetermined number N of the first blocks, where N is an integer of 1or more, processing performed by the compressor includes reference-typeprocessing that uses, as a reference object, a first block that is notset to a compression object among the first blocks, and the input buffermemory stores the image data of a first block that is scheduled to beused as either the compression object or the reference object, and freesa storage area allocated to a first block that is no longer scheduled tobe used as either the compression object or the reference object, at apredetermined timing.

A data storage control apparatus according to a twenty-first aspect ofthe present invention is the data storage control apparatus of thetwentieth aspect in which the compressor acquires the image data inunits of third blocks, each including a predetermined number X of thesecond blocks, where X is an integer of 1 or more, from the input buffermemory, and the input buffer memory manages the storage area inassociation with the third blocks.

A data storage control apparatus according to a twenty-second aspect ofthe present invention is the data storage control apparatus of eitherthe twentieth or twenty-first aspect that further includes an outputbuffer memory that temporarily stores the write data that is output fromthe compressor for the supply to the writing controller. The memoryincludes a plurality of banks, and the writing controller writes thewrite data to the memory while switching the plurality of banks everypiece of the write data.

A data storage control apparatus according to a twenty-third aspect ofthe present invention is the data storage control apparatus of thetwenty-second aspect in which the writing controller waits for Y banks'worth of the write data to be accumulated in the output buffer memory,where Y is an integer of 2 or more, and collectively writes the Y banks'worth of the write data to the memory.

A data storage control apparatus according to a twenty-fourth aspect ofthe present invention is the data storage control apparatus of one ofthe twentieth to twenty-third aspects in which upstream of the inputbuffer memory, image processing is performed in units of macroblocks,and a predetermined number V of the second blocks corresponds to apredetermined number W of the microblocks, where V and W are integers of1 or more.

A data storage control method according to a twenty-fifth aspect of thepresent invention includes (a) compressing image data and outputtingcompressed data, (b) writing the compressed data as write data to amemory, and (c) temporarily storing the image data used in the step (a)in an input buffer memory. The step (a) includes compressing the imagedata in units of first blocks, each being an image block of apredetermined area size, and outputting the compressed data in units ofsecond blocks, each including a predetermined number N of the firstblocks, where N is an integer of 1 or more. The step (a) includesreference-type processing that uses, as a reference object, a firstblock that is not set to a compression object among the first blocks.The step (c) includes storing the image data of a first block that isscheduled to be used as either the compression object or the referenceobject in the input buffer memory, and freeing a storage area of theinput buffer memory that is allocated to a first block that is no longerscheduled to be used as either the compression object or the referenceobject, at a predetermined timing.

According to the above-described first and nineteenth aspects, the useamount of memory capacity can more reliably be reduced. The same effectcan also be achieved by the second to eighteenth aspects that are basedon the first aspect.

According to the above-described twentieth and twenty-fifth aspects, theinput buffer memory can be used efficiently. The same effect can also beachieved by the twenty-first to twenty-fourth aspects that are based onthe twentieth aspect.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an encoding apparatus accordingto a first preferred embodiment;

FIG. 2 is a block diagram illustrating a data storage control apparatusaccording to the first preferred embodiment;

FIG. 3 illustrates processing blocks (for a Y component) according tothe first preferred embodiment;

FIG. 4 illustrates processing blocks (for Cb and Cr components)according to the first preferred embodiment;

FIG. 5 is a block diagram illustrating an example of a losslesscompressor according to the first preferred embodiment;

FIG. 6 is a conceptual diagram illustrating a first example of losslesscompression according to the first preferred embodiment;

FIG. 7 is a block diagram illustrating an example of a lossy compressoraccording to the first preferred embodiment;

FIG. 8 is a block diagram illustrating a first example of a lossycompression processor according to the first preferred embodiment;

FIG. 9 illustrates the first example of the lossy compression processoraccording to the first preferred embodiment;

FIG. 10 is a block diagram illustrating a second example of the lossycompression processor according to the first preferred embodiment;

FIG. 11 is a block diagram illustrating a third example of the lossycompression processor according to the first preferred embodiment;

FIG. 12 is a block diagram illustrating a fourth example of the lossycompression processor according to the first preferred embodiment;

FIG. 13 is a block diagram illustrating an example of a compressed datagenerator according to the first preferred embodiment;

FIG. 14 illustrates an example of computation using a weak LPF accordingto the first preferred embodiment;

FIG. 15 illustrates an example of computation using a strong LPFaccording to the first preferred embodiment;

FIG. 16 illustrates an example of a hierarchy of information maintainingaccuracy according to the first preferred embodiment;

FIG. 17 illustrates a first example of numerical values (for the Ycomponent) according to the first preferred embodiment;

FIG. 18 illustrates the first example of numerical values (for the Cbcomponent) according to the first preferred embodiment;

FIG. 19 illustrates the first example of numerical values (for the Crcomponent) according to the first preferred embodiment;

FIGS. 20 to 27 illustrate a second example of numerical values accordingto the first preferred embodiment;

FIG. 28 is a conceptual diagram illustrating a second example oflossless compression according to the first preferred embodiment;

FIGS. 29 to 36 illustrate a third example of numerical values accordingto the first preferred embodiment;

FIG. 37 is a block diagram illustrating a fifth example of the lossycompression processor according to the first preferred embodiment;

FIG. 38 is a conceptual diagram illustrating the fifth example of thelossy compression processor according to the first preferred embodiment;

FIGS. 39 and 40 illustrate an example of numerical values with the fifthexample of the lossy compression processor according to the firstpreferred embodiment;

FIG. 41 is a block diagram illustrating a data readout control apparatusaccording to the first preferred embodiment;

FIG. 42 illustrates a data configuration according to a second preferredembodiment;

FIG. 43 illustrates a first example of data transfer control accordingto the second preferred embodiment;

FIG. 44 illustrates a second example of data transfer control accordingto the second preferred embodiment; and

FIG. 45 illustrates a third example of data transfer control accordingto the second preferred embodiment.

DESCRIPTION OF PREFERRED EMBODIMENTS First Preferred Embodiment

Encoding Apparatus

FIG. 1 is a block diagram illustrating an example of an encodingapparatus 1 according to a first preferred embodiment. The encodingapparatus 1 is configured to be compliant with a format such as H.264,Moving Picture Experts Group-2 (MPEG-2), and MPEG-4, and performscompression processing (in other words, encoding processing) on movingimage data.

In the example in FIG. 1, a motion predictor 4 reads out image data tobe encoded from a storage unit 2, reads out reference image data to beused in motion prediction from storage unit 3, and performs a motionprediction on the basis of these image data. The motion prediction isperformed in units of so-called macroblocks. Here, an example is givenin which the storage units 2 and 3 are static random access memories(SRAMs), and the storage unit 2 and storage unit 3 are also referred toas “SRAM 2” and “SRAM 3”, respectively.

Data resulting from the motion prediction is transformed by atransformer 5 using, for example, a discrete cosine transform (DCT)technique. The transformer 5 further quantizes resultant transformcoefficients (so-called DCT coefficients). The quantized transformcoefficients are encoded by an entropy coder 6 using entropy coding, andoutput as a bit stream of compressed image data from the entropy coder6. Note that the entropy coding uses a technique such as context-basedadaptive binary arithmetic coding (CABAC) or context-based adaptivevariable length coding (CAVLC).

The quantized transform coefficients are also supplied to an inversetransformer 7. The inverse transformer 7 performs the oppositeprocessing to that of the transformer 5, i.e., inverse quantization andinverse DCT, to generate a residual signal about a result of the motionprediction. The residual signal is combined with predicted image datasupplied from the motion predictor 4, and then input to a deblockingfilter 8. The deblocking filter 8 performs deblocking processing, i.e.,processing for reducing block noise that occurs at boundaries betweenmicroblocks.

Deblocked image data is stored in a storage unit 10 by a data storagecontrol apparatus 9. Here, an example is given in which the storage unit10 is a dynamic random access memory (DRAM), and the storage unit 10 isalso referred to as a “DRAM 10.” Image data stored in the DRAM 10 isread out by a data readout control apparatus 11 and stored as referenceimage data in the SRAM 3.

The data storage control apparatus 9 compresses the reference image data(more specifically, deblocked reference image data in the example inFIG. 1), which is generated within the encoding apparatus 1, beforestoring it in the DRAM 10. On the other hand, the data readout controlapparatus 11 reconstructs the compressed data stored in the DRAM 10,before storing it in the SRAM 3. Note that the data storage controlapparatus 9 and the data readout control apparatus 11 are alsoapplicable to apparatuses that have different configurations from thatin the example in FIG. 1.

Overview of Data Storage Control Apparatus

FIG. 2 is a block diagram illustrating an example of the data storagecontrol apparatus 9. In the example in FIG. 2, the data storage controlapparatus 9 includes an input buffer memory 31, a compressor 32, anoutput buffer memory 33, and a writing controller 34. In the followingdescription, the buffer memory is also simply referred to as “buffer.”

The input buffer 31 is configured of an SRAM, for example. The inputbuffer 31 temporarily stores image data to be supplied to the compressor32. In the present example, the image data to be supplied to thecompressor 32 is reference image data (more specifically, deblockedreference image data).

Here, an example is given in which an image is represented by Y, Cb, andCr components. In this case, image data refers to each of image data ofthe Y component, image data of the Cb component, and image data of theCr component. Note that the data storage control apparatus 9 is alsoapplicable to examples in which the image is represented by othercomponents.

The compressor 32 includes a compressed data generator 41 and a selector42.

The compressed data generator 41 is configured to be capable ofgenerating a plurality of types of compressed data from the image dataacquired via the input buffer 31. More specifically, the compressed datagenerator 41 includes a lossless compressor 51 that performs losslesscompression and a lossy compressor 52 that performs lossy compression.Note that lossless compression is also called “reversible compression,”and lossy compression is also called “irreversible compression.”

The compressed data generator 41 causes the lossless compressor 51 andthe lossy compressor 52 to compress image data and generate a pluralityof types of compressed data. The compressed data generator 41 may beconfigured to generate some or all of the plurality of types ofcompressed data in parallel (in other words, simultaneously), or may beconfigured to generate them in series (in other words, sequentially).

The selector 42 performs predetermined selection processing on varioustypes of compressed data generated by the compressed data generator 41.Specifically, the selection processing involves determining whether eachtype of compressed data generated by the compressed data generator 41satisfies a predetermined selection condition, and selecting one pieceof compressed data that satisfies the predetermined selection condition.

The above selection condition includes a data size condition and a dataaccuracy condition. The data size condition is that the data size isless than or equal to a predetermined value. The data accuracy conditionis that information maintaining accuracy is highest among compresseddata pieces that satisfy the data size condition. The informationmaintaining accuracy expresses to what extent information provided byuncompressed image data is maintained after compression andreconstruction. The information maintaining accuracy may be referred toas reconstruction accuracy.

The output buffer 33 temporarily stores compressed data selected by theselector 42, i.e., compressed data output from the compressor 32, andsupplies the stored data to the writing controller 34.

The writing controller 34 writes the compressed data stored in theoutput buffer 33 as write data to the storage unit 10 (see FIG. 1). Inthe example where the storage unit 10 is a DRAM, the writing controller34 may be configured of a so-called DRAM controller. In the followingdescription, the writing controller 34 is thus also referred to as a“DRAM controller 34.”

Here, the data storage control apparatus 9 processes image data in unitsof image blocks. Such processing blocks are illustrated in FIGS. 3 and4. FIG. 3 illustrates image data of the Y component, and FIG. 4illustrates image data of the Cb and Cr components. As illustrated inFIGS. 3 and 4, the data storage control apparatus 9 uses two types ofimage blocks, namely, first blocks BL1 and second blocks BL2.

Here, an example is given in which the image data of the Y component(see FIG. 3) includes first blocks BL1 that each have an area size of4×1 pixels, and second blocks BL2 that each have an area size of 16×4pixels. In this case, the second blocks BL2 each include 4×4 firstblocks BL1. In other words, the second blocks BL2 each can be dividedinto 16 first blocks BL1.

Also, an example is given in which the image data of the Cb and Crcomponents (see FIG. 4) includes first blocks BL1 that each have an areasize of 8×1 pixels, and second blocks BL2 that each have an area size of8×2 pixels. In this case, the second blocks BL2 each include 1×2 firstblocks BL1. In other words, the second blocks BL2 each can be dividedinto two first blocks BL1.

The second blocks BL2 each include N (N is an integer of 1 or more)first blocks BL1, and in the examples in FIGS. 3 and 4, N is 2 or more.Alternatively, N may be 1, in which case the second blocks BL2 have thesame area size as the first blocks BL1.

Note that a macroblock MB (see FIGS. 3 and 4) used in formats such asH.264 and MPEG is set to have an area size of 16×16 or 8×8 pixels, forexample. When the encoding apparatus 1 is compliant with formats such asH.264 and MPEG, for example, the input buffer 31 receives input of imagedata in units of such macroblocks MB.

For example, the compressed data generator 41 performs losslesscompression and lossy compression on each of the first blocks BL1, andthe selector 42, for example, performs selection processing on each ofthe second blocks BL2.

The following describes a more specific example of the data storagecontrol apparatus 9.

Lossless Compressor

FIG. 5 illustrates an example of the lossless compressor 51. In theexample in FIG. 5, the lossless compressor 51 includes a losslesscompression processor 61 that performs predetermined losslesscompression in units of first blocks BL1.

FIG. 6 illustrates an example of lossless compression performed by thelossless compression processor 61. FIG. 6 illustrates a first block BL1of the Y component, and for ease of description, four pixels PX thatconstitute the first block BL1 are respectively referred to as PXa, PXb,PXc, and PXd in order from the left. Pixel values (in other words, pixeldata) P of the pixels PXa, PXb, PXc, and PXd are respectively referredto as Pa, Pb, Pc, and Pd.

In the example in FIG. 6, the pixel value Pa of the pixel PXa remainsunchanged even after compression. On the other hand, the pixel value ofthe pixel PXb is converted to {Pb−Pa}, the pixel value of the pixel PXcis converted to {Pc−Pb}, and the pixel value of the pixel PXd isconverted to {Pd−Pc}.

Specifically, the lossless compression processor 61 sequentially definesa compression target pixel and a standard pixel according to a pixelclassification in which pairs of pixels PX adjacent to each other in thefirst block BL1 are defined with one pixel as a compression target pixeland the other pixel as a standard pixel, and these pairs of pixels aresequentially selected in the first block BL1. The lossless compressionprocessor 61 then performs lossless compression, which involvesobtaining a difference in pixel value between the compression targetpixel and the standard pixel and assigning the resultant differencevalue to the compression target pixel. While, in the example in FIG. 6,the left pixel PX among these pairs of pixels PX is set as the standardpixel, the right pixel PX may be set as the standard pixel. Note thatthe same lossless compression can also be performed on the image data ofthe Cb and Cr components.

Note that the lossless compression processor 61 may adopt other types oflossless compression. Alternatively, the lossless compressor 51 mayinclude a plurality of lossless compression processors 61 that performdifferent types of lossless compression.

Lossy Compressor

FIG. 7 illustrates an example of the lossy compressor 52. In the examplein FIG. 7, the lossy compressor 52 includes a plurality of lossycompression processors 62 that perform different types of lossycompression. First to fourth examples of the lossy compressionprocessors 62 will now be described with reference to FIGS. 8 to 12.

As illustrated in FIG. 8, a lossy compression processor 62 a accordingto the first example generates compressed data by performing processingusing a low-pass filter (LPF), i.e., low-pass processing, on compressiontarget data. The low-pass processing is one type of lossy compression.One example of a low-pass filter is a horizontal low-pass filter.

As an example, a 9-tap horizontal low-pass filter will be described withreference to FIG. 9. Here, assumed that a pixel of interest has a pixelvalue P4, the four pixels on the left side of the pixel of interestrespectively have pixel values P0 to P3, and the four pixels on theright side of the pixel of interest respectively have pixel values P5 toP8. It is also assumed that these nine pixels have LPF coefficients C0to C8. In this case, the pixel of interest that has undergone low-passprocessing is assigned a value that is calculated from the equation inFIG. 9.

By sequentially setting each pixel in the first block BL1 as a pixel ofinterest, the low-pass processing on the first block BL1 is completed.Note that in the example in FIG. 9, pixel values in other first blocksBL1 that are adjacent to the first block BL1 to be compressed are alsoreferenced.

As illustrated in FIG. 10, a lossy compression processor 62 b accordingto the second example generates compressed data by performing low-passprocessing and lossless compression in this order on compression targetdata. Here, it is assumed that the low-pass processing is the same asthat performed by the lossy compression processor 62 a (see FIG. 8), andthe lossless compression is the same as that performed by the losslesscompression processor 61 (see FIG. 5).

As illustrated in FIG. 11, a lossy compression processor 62 c accordingto the third example generates compressed data by performing low-passprocessing, lossless compression, and a bit shift processing in thisorder on compression target data. Here, it is assumed that the low-passprocessing and the lossless compression are the same as those performedby the lossy compression processor 62 b (see FIG. 10). The bit shiftprocessing involves shifting difference values obtained from thelossless compression (more specifically, a bit string obtained byrepresenting the difference values in binary) by a predetermined shiftamount toward the least significant bit (LSB). In the followingdescription, a bit shift toward the least significant bit is alsoreferred to as a “right bit shift” or a “right shift.”

Using different shift amounts makes it possible to generate a pluralityof pieces of compressed data from one piece of compression target data,as in a lossy compression processor 62 d (see FIG. 12) according to thefourth example.

The lossy compression processors 62 may also adopt configurations otherthan those in the first to fourth examples. For example, the lossycompression processors 62 b to 62 d may omit the LPF processing (seeFIGS. 10 to 12). Also, changing the strength of the LPF can configureanother lossy compression processor 62. Note that the strength of theLPF is adjustable by controlling the LPF coefficients.

Specific Example of Compressed Data Generator

FIG. 13 is a block diagram illustrating an example of the compresseddata generator 41. In the example in FIG. 13, the lossless compressor 51is assumed to be configured as in the examples in FIGS. 5 and 6. In theexample in FIG. 13, the lossy compressor 52 includes four lossycompression processors 62.

Specifically, the four lossy compression processors 62 include two lossycompression processors 62 b 1 and 62 b 2 that are each configured by thelossy compression processor 62 b (see FIG. 10), and two lossycompression processors 62 d 1 and 62 d 2 that are each configured as thelossy compression processor 62 d (see FIG. 12). The lossy compressionprocessors 62 b 1 and 62 d 1 share an execution part that performslow-pass processing and lossless compression. A bit shift processing onan output of the lossy compression processor 62 b 1 generates an outputof the lossy compression processor 62 d 1. Similarly, the lossycompression processors 62 b 2 and 62 d 2 share an execution part thatperforms low-pass processing and lossless compression. The LPF shared bythe lossy compression processors 62 b 1 and 62 d 1 has a lower strengththan the LPF shared by the lossy compression processors 62 b 2 and 62 d2. FIG. 14 illustrates computation using the weak LPF, and FIG. 15illustrates computation using the strong LPF.

Here, compressed data that is generated by the lossless compressionprocessor 61 is referred to as “Da” as illustrated in FIG. 13.

Also, compressed data that is generated by the lossy compressionprocessor 62 b 1 having the weak LPF is referred to as “Db.” The twopieces of compressed data that are generated by the lossy compressionprocessor 62 d 1 having the weak LPF are referred to as “Dc” and “Dd.”The compressed data Dc is obtained by shifting the compressed data Db byone bit to the right, and the compressed data Dd is obtained by shiftingthe compressed data Db by two bits to the right.

Also, compressed data that is generated by the lossy compressionprocessor 62 b 2 having the strong LPF is referred to as “De.” The twopieces of compressed data that are generated by the lossy compressionprocessor 62 d 2 having the strong LPF are referred to as “Df” and “Dg.”The compressed data Df is obtained by shifting the compressed data De byone bit to the right, and the compressed data Dg is obtained by shiftingthe compressed data De by two bits to the right.

The following is a more specific description of the operation performedby the compressor 32 with reference to the example in FIG. 13.

Exemplary Operation of Compressor

In the compressor 32, as described above, the compressed data generator41 generates a plurality of types of compressed data from a single pieceof image data, and the selector 42 selects one of the plurality of typesof compressed data. The selection processing performed by the selector42 uses the data size condition and the data accuracy condition.

First, the data accuracy condition will be described. As describedabove, the data accuracy condition is that the information maintainingaccuracy is highest among compressed data that satisfy the data sizecondition. It is assumed that a hierarchy of the information maintainingaccuracy is predetermined through simulation, testing, or the like,which is performed in advance, and information about the hierarchy isprovided in advance to the selector 42.

Hereinafter, an example in FIG. 16 will be referenced with regard to thehierarchy of the information maintaining accuracy of the compressed datapieces Da to Dg (see FIG. 13). In the example in FIG. 16, the losslesslycompressed data Da has the highest information maintaining accuracy. Theinformation maintaining accuracy decreases in the order of the lossycompressed data pieces Db, De, Dc, Df, and Dd, and the lossy compresseddata Dg has the lowest information maintaining accuracy.

Next, the data size condition will be described. As described above, thedata size condition is that the data size of compressed data is lessthan or equal to a predetermined value. More specifically, the data sizecondition requires all first blocks BL1 included in a second block BL2used in selection processing to have a data size less than or equal tothe predetermined value. A specific example of the data size conditionwill now be described with reference to examples of numerical values inFIGS. 17 to 19.

In FIG. 17 and subsequent drawings, four numerical values in each firstblock BL1 indicate data (in other words, pixel values) of the fourpixels of the first block BL1. FIGS. 17, 18, and 19 respectivelyillustrate image data of the Y component, image data of the Cbcomponent, and image data of the Cr component. The examples applylossless compression using the technique of FIG. 6 to generate thelosslessly compressed data Da. Note that the compressed data generator41 may be configured to process some or all of the first blocks BL1 inthe second block BL2 in parallel, or may be configured to generate themin series.

In the compressed data, the pixels of the first blocks BL1 areclassified into determination target pixels (pixels on whichdetermination is to be performed) and excluded pixels (pixels to beexcluded from the determination). In FIGS. 17 to 19, excluded pixels areshaded with small dots. In FIG. 17, the pixel at the left end of eachfirst block BL1 is set as an excluded pixel, and the other three pixelsare set as determination target pixels. In FIGS. 18 and 19, the pixel atthe left end of each first block BL1 is set as an excluded pixel, andthe other seven pixels are set as determination target pixels. In otherwords, pixels that are used as only standard pixels in losslesscompression are set as excluded pixels.

The data size condition requires the pixel value of each determinationtarget pixel (here, a difference value obtained from the losslesscompression) to be represented by a predetermined number of bits orless. The predetermined number of bits is set to a value smaller thanthe number of bits (in the present example, 8 bits) assigned torepresent each pixel value in compression target data (i.e., image datainput to the compressor 32).

As one example, the predetermined number of bits for image data of the Ycomponent is assumed to be 5 bits. In this case, the data size conditionrequires the pixel value of each determination target pixel to fallwithin a range of numerical values that can be represented by 5 bits(i.e., in the range of −16 to +15). Note that a negative number isrepresented in two's complement notation. As an example, thepredetermined number of bits for image data of the Cb and Cb componentsis assumed to be 4 bits. In this case, the data size condition requiresthe pixel value of each determination target pixel to fall within arange of numerical values that can be represented by 4 bits (i.e., inthe range of −8 to +7).

The examples in FIGS. 17 to 19 show that the pixel values of thedetermination target pixels in all of the first blocks BL1 can berepresented by the predetermined numbers of bits or less. Consequently,the examples in FIGS. 17 to 19 satisfy the data size condition.

In the examples in FIGS. 17 to 19, the losslessly compressed data Da isgenerated. As described above, the losslessly compressed data Da has thehighest information maintaining accuracy (see FIG. 16). Accordingly, inthe examples in FIGS. 17 to 19, the compressed data Da satisfies boththe data size condition and the data accuracy condition. Consequently,the compressed data Da is selected by the selector 42 and output fromthe compressor 32.

The data size of the uncompressed second block BL2 is calculated asfollows. The data size of the Y component is 512 bits (={8 bits×4pixels}×16 blocks), the data size of the Cb component is 128 bits (={8bits×8 pixels}×2 blocks), and the data size of the Cr component is also128 bits. Thus, the total number of bits is 768 bits.

On the other hand, the data size of the compressed second block BL2 thatsatisfies the data size condition is calculated as follows. The datasize of the Y component is 368 bits (={8 bits×1 pixel+5 bits×3pixels}×16 blocks), the data size of the Cb component is 72 bits (={8bits×1 pixel+4 bits×7 pixels}×2 blocks), and the data size of the Crcomponent is also 72 bits. Thus, the total number of bits is 512 bits.

That is, when the data size condition is satisfied, the second block BL2can be compressed from 768 bits to 512 bits.

Next, another example of numerical values will be described withreference to FIGS. 20 to 25. Although only the Y component isillustrated in FIGS. 20 to 25, the same procedure can also be applied tothe Cb and Cr components.

In FIG. 20, lossless compression is performed on compression target data(i.e., image data input to the compressor 32) to generate losslesslycompressed data Da (see FIG. 13).

In FIG. 21, low-pass processing using a weak LPF and losslesscompression are performed in this order on the compression target datato generate lossy compressed data Db (see FIG. 13). Note that thelow-pass processing performed on first blocks BL1 at the left and rightends of the second block BL2 uses first blocks BL1 of adjacent secondblocks BL2 (see first blocks BL1 indicated by dashed double-dotted linesin FIG. 22), as described with reference to FIG. 9.

FIG. 23 illustrates lossy compressed data Dc that is generated byperforming low-pass processing using a weak LPF, lossless compression,and a right bit shift (by one bit) in this order on the compressiontarget data (see FIG. 13). Note that lossy compressed data Dd that isgenerated through a right 2-bit shift is not shown.

In FIG. 24, low-pass processing using a strong LPF and losslesscompression are performed in this order on the compression target datato generate lossy compressed data De (see FIG. 13). FIG. 25 illustrateslossy compressed data Df that is generated by performing low-passprocessing using a strong LPF, lossless compression, and a right bitshift (by one bits) in this order on the compression target data (seeFIG. 13). Note that lossy compressed data Dg that is generated through aright 2-bit shift is not shown.

In the examples in FIGS. 20 to 25, pixel values enclosed by circles inthe compressed data pieces Da, Db, Dc, and De do not fall within therange of numerical values that can be represented by 5 bits (i.e., inthe range of −16 to +15). This indicates that the compressed data piecesDa, Db, Dc, and De do not satisfy the data size condition. On the otherhand, it can be seen from FIG. 25 that the compressed data Df satisfiesthe data size condition. In this case, the compressed data Df has thehighest information maintaining accuracy among pieces of compressed datathat satisfy the data size condition, with reference to FIG. 16. Thatis, the compressed data Df also satisfies the data accuracy condition.Accordingly, the compressed data Df is selected by the selector 42 andoutput from the compressor 32.

FIG. 26 illustrates image data that is obtained by reconstructing thecompressed data Df. FIG. 27 illustrates errors between the uncompressedimage data and the image data obtained by reconstructing the compresseddata Df. In the example in FIG. 27, the sum of absolute values of theerrors is 40.

Here, it is efficient to perform the data size condition determinationin descending hierarchy of the information maintaining accuracy among aplurality of types of compressed data generated by the compressed datagenerator 41. This is because finding compressed data that satisfies thedata size condition will eliminate the need to perform the data sizecondition determination for the remaining compressed data. In addition,for example in the case where the compressed data generator 41 generatesa plurality of types of compressed data in series, finding compresseddata that satisfies the data size condition will eliminate the need togenerate the remaining compressed data for the second block BL2.

Note that if the predetermined number of bits in the data size conditionis M bits, compressed data that satisfies the data size condition canreliably be generated by providing a bit shift processing with a shiftamount of {8−M} bits.

Another Example of Lossless Compression

With the lossless compression described with reference to FIG. 6, aleft-side pixel, excluding the pixel at the left end, is set as astandard pixel, and a difference in pixel value between the two pixelsis calculated. With this technique, a small difference value is readilyobtained. Consequently, it is possible to reduce the shift amount in thebit shift processing, in other words, to reduce the number of steps inthe bit shift processing.

On the other hand, if the lossy compression processor 62 uses thelossless compression in FIG. 6, errors may accumulate toward the rightside of the first block BL1, in other words, errors may diffuse to theright side in the first block BL1.

In contrast, a lossless compression illustrated in FIG. 28 can suppressdiffusion of errors. Specifically, the pixel value Pa of the pixel PXaremains unchanged even after compression according to the example inFIG. 28. On the other hand, the pixel value of the pixel PXb isconverted to {Pb−Pa}, the pixel value of the pixel PXc is converted to{Pc−Pa}, and the pixel value of the pixel PXd is converted to {Pd−Pa}.

That is, although the example in FIG. 28 illustrates the same content ofprocessing for calculating differences in pixel value as that in FIG. 6,the definitions of the pixel classifications are different.Specifically, the pixel classification which is adopted in the examplein FIG. 28 is such that a pixel PX at a predetermined fixed position inthe first block BL1 is defined as a standard pixel, and the remainingpixels PX at positions other than the fixed position in the first blockBL1 are defined as compression target pixels. While the example in FIG.28 defines the left end of the first block BL1 as the fixed position,the fixed position may be any other position. Note that similar losslesscompression can also be performed on the image data of the Cb and Crcomponents.

FIGS. 29 to 34 illustrate examples of numerical values in the case ofusing the lossless compression in FIG. 28. Although only the Y componentis illustrated in FIGS. 29 to 34, the same procedure can also be appliedto the Cb and Cr components.

In FIG. 29, low-pass processing using a weak LPF and losslesscompression in FIG. 28 are performed in this order on compression targetdata to generate lossy compressed data Db (see FIG. 13). FIG. 30illustrates lossy compressed data Dc that is generated by performinglow-pass processing using a weak LPF, lossless compression in FIG. 28,and a right bit shift (by one bit) in this order on the compressiontarget data (see FIG. 13). FIG. 31 illustrates lossy compressed data Ddthat is generated through a right 2-bit shift (see FIG. 13).

In FIG. 32, low-pass processing using a strong LPF and losslesscompression in FIG. 28 are performed in this order on the compressiontarget data to generate lossy compressed data De (see FIG. 13). FIG. 33illustrates lossy compressed data Df that is generated by performinglow-pass processing using a strong LPF, lossless compression in FIG. 28,and a right bit shift (by one bit) in this order on the compressiontarget data (see FIG. 13). FIG. 34 illustrates lossy compressed data Dgthat is generated through a right 2-bit shift (see FIG. 13).

The examples in FIGS. 29 to 34 show that the compressed data Dgsatisfies both the data size condition and the data accuracy condition.Accordingly, the compressed data Dg is selected by the selector 42 andoutput from the compressor 32.

FIG. 35 illustrates image data that is obtained by reconstructing thecompressed data Dg in FIG. 34. FIG. 36 illustrates errors between theuncompressed image data and the image data obtained by reconstructingthe compressed data Dg. In the example in FIG. 36, the sum of absolutevalues of the errors is 60.

Here, the lossless compressor 51 and the lossy compressor 52 are assumedto adopt the same lossless compression, but the present invention is notlimited to this example. For example, the lossless compressor 51 mayadopt the technique in FIG. 6, and the lossy compressor 52 may adopt thetechnique in FIG. 28. In the case where the lossy compressor 52 includesa plurality of lossy compression processors 62, some or all of the lossycompression processors 62 may adopt a lossless compression that isdifferent from the technique adopted by the lossless compressionprocessor 61. Using the same lossless compression technique simplifiesapparatus design, for example. In addition, it is possible to share thecircuit to be used in lossless compression. On the other hand, usingdifferent lossless compression techniques makes it possible to adjustthe information maintaining accuracy and to thereby increase the degreeof freedom of apparatus design.

Another Example of Lossy Compression

Yet another example of the lossy compression processors 62 will bedescribed with reference to FIGS. 37 and 38. A lossy compressionprocessor 62 e in FIG. 37 generates compressed data by performing abit-reduction processing on compression target pixels in compressiontarget data. In the bit-reduction processing, the number of bits in eachpixel value is reduced by deleting a predetermined range of bits fromthe least significant bit (LSB) of the bit string, which represents thepixel value, as illustrated in FIG. 38.

FIG. 38 illustrates an example in which an uncompressed pixel value isrepresented by “01011001” in binary notation (or “89” in decimalnotation), and the least significant three bits are deleted. In otherwords, the most significant five bits “01011” are extracted ascompressed data and output from the lossy compression processor 62 e.

Here, extracting the most significant five bits makes it possible forthe pixel value of the compression target pixel to reliably fit in therange of numerical values that can be represented by five bits (i.e., inthe range of −16 to +15).

FIG. 39 shows an example of numerical values when compressed datagenerated from the bit-reduction processing is reconstructed. Note thatthe reconstruction processing is processing for combining “000” as theleast significant three bits with the compressed pixel value consistingof five bits. FIG. 40 illustrates errors in image data before and aftercompression. In the example in FIG. 40, the sum of absolute values ofthe errors is 236.

In the example in FIG. 39, all pixels in the second block BL2 are set ascompression target pixels. This can simplify apparatus design, forexample. Alternatively, only three pixels on the right side of eachfirst block BL1 may be set as compression target pixels. In either case,compression target pixels are set as determination target pixels used inthe selector 42.

Note that the same bit-reduction processing is also applicable to the Cband Cr components. Alternatively, the lossy compression processor 62 ethat performs bit-reduction processing may be combined with other lossycompression processors. As another alternative, another lossycompression processor 62 may be configured by combining bit-reductionprocessing with various types of processing (see FIGS. 10 to 13, forexample).

Advantageous Effects

The data storage control apparatus 9 compresses reference image databefore storing it in the DRAM 10. It is thus possible to reduce the useamount of memory capacity of the DRAM 10.

In addition, the data size of compressed data for each second block BL2,which is output from the compressor 32, is the same irrespective of thetype of compression technique that is used by the compressor 32. Inother words, compressed data output from the compressor 32 has a fixedlength.

If the data size differs for each block, addresses of storage areas needto be managed on the basis of different data sizes to compactly storethe data of each block in the DRAM. If the storage area is divided intoequal areas to match the maximum data size to simplify addressmanagement, the use amount of memory capacity of the DRAM cannot bereduced.

In contrast, the data storage control apparatus 9 causes the compressor32 to output compressed data of the same size as described above. It isthus possible with simple address management to compactly storecompressed data. Compact storage of compressed data contributes to areduction in the use amount of memory capacity of the DRAM 10. Forexample, since the data size of each second block BL2 can be reduced totwo-third (=512 bits/768 bits) as described above, it is possible toreduce the use amount of memory capacity of the DRAM 10 to two-third.

Data Readout Control Apparatus

FIG. 41 is a block diagram illustrating the data readout controlapparatus 11. In the example in FIG. 41, the data readout controlapparatus 11 includes a readout controller 134, an input buffer 131, anda decompressor 132.

The readout controller 134 reads out compressed data stored in thestorage unit 10 (see FIG. 1) and transfers the compressed data to theinput buffer 131. In the case where the storage unit 10 is a DRAM, thereadout controller 134 can be configured as a so-called DRAM controller.In the following description, the readout controller 134 is thus alsoreferred to as the “DRAM controller 134.”

The input buffer 131 is configured of an SRAM, for example. The inputbuffer 131 temporarily stores compressed data to be supplied to thedecompressor 132.

The decompressor 132 decompresses compressed data acquired via the inputbuffer 131. The decompressor 132 includes a decompressed data generator141 and a selector 142. The decompressed data generator 141 includes alossless compressor 151 and a lossy compressor 152. The losslesscompressor 151 and the lossy compressor 152 respectively have the sameconfigurations as the lossless compressor 51 and the lossy compressor 52of the data storage control apparatus 9 (see FIG. 2). The selector 142has the same configuration as the selector 42 of the data storagecontrol apparatus 9.

Accordingly, the decompressed data generator 141 generates a pluralityof types of data from the compressed data read out from the DRAM 10. Theselector 142 selects one piece of data that satisfies a predeterminedselection condition (i.e., a selection condition adopted by the selector42) from among the plurality of types of data. The data selected by theselector 142 is then transferred as decompressed data to the SRAM 3.

Here, the reference image data (in the example in FIG. 1, deblockedreference image data) generated within the encoding apparatus 1 iscompressed by the data storage control apparatus 9, then reconstructedby the data readout control apparatus 11, and then supplied to themotion predictor 4. In this case, to predict motion favorably, an imagethat is the same as, or as close as possible to, the uncompressedreference image (in other words, an image whose error relative to theuncompressed reference image is within a tolerance) is preferablysupplied to the motion predictor 4. Note that the tolerance is, forexample, preset through simulation, testing or the like, which isperformed in advance.

For example, assume the case in which the compressed data generator 41and the decompressed data generator 141 adopt the configuration in FIG.13. In this case, to the compressed data pieces Dc, Dd, Df, and Dg thathave undergone a bit shift processing can provide a reference image thatis within a tolerance by the decompression using the same technique asthat used in compression. On the other hand, the compressed data piecesDa, Db, and De that do not undergo the bit shift processing can providea reference image within a tolerance by any decompression technique. Inlight of this, with regard to the compressed data pieces Dc, Dd, Df, andDg that have undergone the bit shift processing, it is preferable forthe selector 142 of the decompressor 132 to be instructed as to whichdecompressed data to select.

The selection instruction may be provided by the selector 42 of thecompressor 32 generating additional information about the compresseddata that has been selected and storing the additional informationassociated with the compressed data in the DRAM 10. The additionalinformation stored in the DRAM 10 is read out along with the compresseddata by the data readout control apparatus 11 and supplied to theselector 142. This enables the selector 142 to operate in accordancewith the selection instruction included in the additional information.

The additional information may be configured as a 3-bit flag, forexample. More specifically, one bit of the three-bit flag indicates thepresence or absence of a selection instruction to be given to theselector 142 of the decompressor 132. The remaining two bits serve as anidentifier that indicates which one of the compressed data pieces Dc,Dd, Df, and Dg corresponds to compressed data, i.e., a specificinstruction that indicates which decompressed data to select. Note thatthe number of bits allocated for the identifier may be determinedaccording to the number of compressed data pieces used foridentification.

Note that the configuration of the additional information is not limitedto the above example. In the DRAM 10, the area for storing theadditional information may be continuous to the area for storing thecorresponding compressed data, or it may be separated from the area forstoring the corresponding compressed data. For example, the DRAM 10 mayhave an area for storing only the additional information

In the present example, each second block BL2 is compressed to a fixedlength (e.g., 512 bits) as described above. The additional informationis generated for each second block BL2 and has a data size of only 3bits or so in the above-described example. Thus, the data storagecontrol apparatus 9 that adopts the additional information can achievethe same effects as described above.

Second Preferred Embodiment

A second preferred embodiment describes data transfer control in thedata storage control apparatus 9.

As described in the first preferred embodiment, low-pass processing usedin lossy compression involves referencing pixel values of first blocksBL1 that are adjacent to a first block BL1 to be compressed (see FIGS. 9and 22). In other words, the low-pass processing is one example ofreference-type processing that uses, as reference object, first blockBL1 that is not set to a compression object.

In this case, the input buffer 31 needs to store not only image data ofthe first blocks BL1 that are scheduled to be used as compressionobjects but also image data of first blocks BL1 that are scheduled to beused as reference objects.

On the other hand, the input buffer 31 can delete image data of a firstblock BL1 that is no longer scheduled to be used as either a compressionobject or a reference object. In other words, the input buffer 31 freesa storage area occupied by image data of a first block BL1 that is nolonger scheduled to be used as either a compression object or areference object, at a predetermined timing after usage (in other words,the storage area can now be overwritten).

This will be described with reference to FIGS. 42 to 45. Note that thefollowing describes image data of the Y component, but the sameprocedure also applies to the Cb and Cr components.

Here, an example is given in which the pixel data of the Y component issupplied to the input buffer 31 in units of macroblocks MB eachincluding 16×16 pixels, and in raster scan order, as illustrated inFIGS. 42 and 43. Note that each macroblock MB is identified by a suffixnumber added to the reference character “MB” as illustrated in FIG. 42.A suffix number is also added to other reference characters.

Assume that the compressor 32 acquires image data in units of thirdblocks, each including X (X is an integer of 1 or more) second blocksBL2, from the input buffer 31. In the example in FIG. 43, a third blockis assumed to be a macroblock MB (i.e., X=4).

In the example in FIG. 43, the input buffer 31 has four storage areas #1to #4. Note that the four storage areas #1 to #4 may be different SRAMs,in which case the four SRAMs are collectively referred to as the “inputbuffer 31.”

In the example in FIG. 43, when low-pass processing is performed on afirst block BL1 included in a macroblock MB_2, macroblocks MB_1 and MB_3that are adjacent to the macroblock MB_2 on either side are used asreference objects. Thus, the input buffer 31 needs to store data of themacroblocks MB_1, MB_2, and MB_3.

At this time, a macroblock MB_0 is no longer being used as either acompression object or a reference object. Thus, the storage area #1 inwhich the macroblock MB_0 is stored is freed from time t2 onwards, thetime t2 being a time at which the macroblock MB_2 is set to acompression object. In the example in FIG. 43, image data of amacroblock MB_4 is stored at a later time t4 in the storage area #1.

In this case, the input buffer memory 31 manages the storage areas #1 to#4 in association with the macroblock MB serving as the aforementionedthird block.

Managing data in the input buffer 31 in this way allows efficient use ofthe input buffer 31. In addition, such cyclic use of the storage areasof the input buffer 31 allows the input buffer 31 to have smallcapacity.

Here, the DRAM 10 has a plurality of (in the present example, eight)banks BK. Thus, the DRAM controller 34 writes write data to the DRAM 10while switching the banks BK every piece of write data. In the examplein FIG. 43, the banks BK are switched every second block BL2.

In the example in FIG. 44, image data is supplied in units of secondblocks BL2 and in raster scan order to the input buffer 31. Thecompressor 32 acquires image data from the input buffer 31 in units ofthird blocks, each including X (X is an integer of 1 or more) secondblocks BL2. In the example in FIG. 44, a third block is assumed to beone second block BL2 (i.e., X=1).

In the example in FIG. 44, when low-pass processing is performed on afirst block BL1 included in a second block BL2_20, second blocks BL2_10and BL2_30 that are adjacent to the second block BL2_20 on either sideare used as reference objects. Thus, the input buffer 31 needs to storeimage data of the second blocks BL2_10, BL2_20, and BL2_30.

At this time, a second block BL2_00 is no longer being used as either acompression object or a reference object. Thus, the storage area #1 inwhich the second block BL2_00 is stored is freed from time t2 onwards,the time t2 being a time at which the second block BL2_20 is set to acompression object. In the example in FIG. 44, image data of a secondblock BL2_40 is stored in the storage area #1 at a later time t4.

In this case as well, the input buffer memory 31 manages the storageareas #1 to #4 in association with the second blocks BL2 serving as theaforementioned third blocks.

In the example in FIG. 44, also the DRAM controller 34 writes write datato the DRAM 10 while switching the banks BK every piece of write data.

Here, in the example in FIG. 44, the DRAM controller 34 writes writedata to the DRAM 10, one bank's worth of write data at a time (i.e., onesecond block BL2 at a time). Alternatively, the DRAM controller 34 maywait for Y banks' worth of write data (Y is an integer of two or more;in the example in FIG. 45, Y=4) to be accumulated in the output buffer33, and may collectively write these Y pieces of write data to the DRAM10.

Upstream of the input buffer 31 (e.g., the deblocking filter 8), imageprocessing is performed in units of macroblocks MB as described above.In the examples in FIGS. 42 to 45, a single macroblock MB corresponds tofour second blocks BL2. In the example in FIG. 43, data is input to theinput buffer 31 in units of four second blocks BL2, whereas in theexamples in FIGS. 44 and 45, data is input in units of one second blockBL2. Meanwhile, in the examples in FIGS. 43 and 45, data is written tothe DRAM 10 in units of four second blocks BL2, whereas in the examplein FIG. 44, data is written in units of one second block BL2.

In light of the above, setting the second blocks BL2 such that a singlemacroblock MB is configured by a plurality of second blocks BL2 preventsgeneration of blocks smaller than the second blocks BL2 (hereinafter,referred to as “small blocks”).

This facilitates management of the storage areas of the input buffer 31at the time of inputting and outputting data to and from the inputbuffer 31. Such facilitated storage management enables efficient use ofthe input buffer 31.

Absence of small blocks at the time of transferring data to the DRAM 10is helpful in efficiently generating transfer data. Further, it ispossible to avoid an increase in bus band that may be caused by the needof transferring small blocks. In other words, it is possible to reducethe bus band. The absence of small blocks also makes it easy for theDRAM controller 34 to manage addresses of the DRAM 10 (in other words,to manage access to the DRAM 10).

Moreover, setting the second blocks BL2 such that a single macroblock MBis configured by a plurality of second blocks BL2 is advantageous infacilitating the introduction of the data storage control apparatus 9 invarious encoding apparatuses that perform image processing in units ofmacroblocks MB.

Here, the above-described effects can also be achieved when a singlemacroblock MB is configured by one second block BL2. The same alsoapplies to the case where a plurality of macroblocks MB correspond to asingle second block BL2. The effects described above can also beachieved when a plurality of macroblocks MB correspond to a plurality ofsecond blocks BL2, i.e., when a plurality of macroblocks MB are regardedas a single block, and this single block is divided into a plurality ofsecond blocks BL2 without producing small blocks mentioned above.

In summary, the above-described effects can be achieved by settingsecond blocks BL2 such that V (V is an integer of 1 or more) secondblocks BL2 correspond to W (W is an integer of 1 or more) macroblocksMB.

Note that the second preferred embodiment is also applicable to the casewhere the compressor 32 adopts a compression technique different fromthat in the first preferred embodiment. The compression technique may bea moving image compression technique or a still image compressiontechnique (e.g., using the Joint Photographic Expert Group (JPEG)format).

The reference-type processing may be other than low-pass processing.Also, the lossless compression may include reference-type processing.

VARIATIONS

The first and second preferred embodiments assume the case in whichvarious types of processing performed by the data storage controlapparatus 9 and the encoding apparatus 1 are all implemented byhardware. In contrast, some or all of the various types of processingmay be implemented by software (in other words, by a microprocessorexecuting a program).

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

What is claimed is:
 1. A data storage control apparatus comprising: acompressor that compresses image data and outputs compressed data; and awriting controller that writes said compressed data as write data to amemory, wherein said compressor includes: a compressed data generatorthat includes a lossless compressor for performing lossless compressionand a lossy compressor for performing lossy compression, and thatcompresses, by using said lossless compressor and said lossy compressor,said image data in units of first blocks, each being an image block of apredetermined area size, to generate a plurality of types of compresseddata in parallel or in series; and a selector that performs selectionprocessing on each second block that includes a predetermined number Nof said first blocks, where N is an integer of 1 or more, said selectionprocessing involving determining whether each of said plurality of typesof compressed data generated by said compressed data generator satisfiesa predetermined selection condition and selecting one piece ofcompressed data that satisfies said predetermined selection condition,said predetermined selection condition includes: a data size conditionthat a data size of all of said first blocks included in said secondblock is less than or equal to a predetermined value; and a dataaccuracy condition that information maintaining accuracy is highestamong said compressed data that satisfies said data size condition, andsaid writing controller writes said one piece of compressed dataselected by said selector as said write data to said memory.
 2. The datastorage control apparatus according to claim 1, wherein said losslesscompression is processing for obtaining a difference in pixel valuebetween a compression target pixel and a standard pixel and assigning aresultant difference value to said compression target pixel, and saidlossless compressor defines said compression target pixel and saidstandard pixel in said first block in accordance with a predeterminedpixel classification and performs said lossless compression on saidcompression target pixel and said standard pixel that have been defined.3. The data storage control apparatus according to claim 2, wherein saidpredetermined pixel classification includes a first pixel classificationaccording to which pairs of pixels are sequentially selected in saidfirst block, each of pairs including pixels adjacent to each other insaid first block that are defined with one pixel as said compressiontarget pixel and the other pixel as said standard pixel.
 4. The datastorage control apparatus according to claim 2, wherein saidpredetermined pixel classification includes a second pixelclassification according to which a pixel at a predetermined fixedposition in said first block is defined as said standard pixel, and eachpixel at a position other than said fixed position in said first blockis defined as said compression target pixel.
 5. The data storage controlapparatus according to claim 2, wherein said lossy compressor includesat least one of: a first lossy compression processor that generatesfirst compressed data by performing first low-pass processing using afirst low-pass filter on compression target data; a second lossycompression processor that generates second compressed data byperforming said first low-pass processing and said lossless compressionin this order on said compression target data; and a third lossycompression processor that generates at least one piece of thirdcompressed data by performing said first low-pass processing and saidlossless compression in this order on said compression target data andperforming a first bit shift processing in which a bit of saiddifference value obtained from said lossless compression is shiftedtoward the least significant bit.
 6. The data storage control apparatusaccording to claim 5, wherein said at least one piece of thirdcompressed data is a plurality of pieces of third compressed data thatare generated by using different shift amounts in said first bit shiftprocessing.
 7. The data storage control apparatus according to claim 5,wherein said lossy compressor further includes at least one of: a fourthlossy compression processor that generates fourth compressed data byperforming second low-pass processing using a second low-pass filter onsaid compression target data, said second low-pass filter having adifferent strength from said first low-pass filter; a fifth lossycompression processor that generates fifth compressed data bysequentially performing said second low-pass processing and saidlossless compression on said compression target data; and a sixth lossycompression processor that generates at least one piece of sixthcompressed data by performing said second low-pass processing and saidlossless compression in this order on said compression target data, andperforming a second bit shift processing in which a bit of saiddifference value obtained from said lossless compression is shiftedtoward the least significant bit.
 8. The data storage control apparatusaccording to claim 7, wherein said at least one piece of sixthcompressed data is a plurality of pieces of sixth compressed data thatare generated by using different shift amounts in said second bit shiftprocessing.
 9. The data storage control apparatus according to claim 1,wherein said lossy compressor includes a seventh lossy compressionprocessor that generates seventh compressed data by performingbit-reduction processing on a compression target pixel in compressiontarget data, said bit-reduction processing involves deleting apredetermined range of bits from the least significant bit side of a bitstring that represents said pixel value to reduce the number of bits ofsaid pixel value, and said predetermined range is set such that saidseventh compressed data always satisfies said data size condition. 10.The data storage control apparatus according to claim 1, wherein saidlossless compressor and said lossy compressor operate in parallel. 11.The data storage control apparatus according to claim 1, furthercomprising: an input buffer memory that temporarily stores said imagedata that is to be supplied to said compressor, wherein said losslesscompression or said lossy compression includes reference-type processingthat uses, as a reference object, a first block that is not set to acompression object among said first blocks, and said input buffer memorystores said image data of a first block that is scheduled to be used aseither said compression object or said reference object, and frees astorage area allocated to a first block that is no longer scheduled tobe used as either said compression object or said reference object, at apredetermined timing.
 12. The data storage control apparatus accordingto claim 11, wherein said compressor acquires said image data in unitsof third blocks, each including a predetermined number X of said secondblocks, where X is an integer of 1 or more, from said input buffermemory, and said input buffer memory manages said storage area inassociation with said third blocks.
 13. The data storage controlapparatus according to claim 11, further comprising: an output buffermemory that temporarily stores said write data that is output from saidcompressor for the supply to said writing controller, wherein saidmemory includes a plurality of banks, and said writing controller writessaid write data to said memory while switching said plurality of banksevery piece of said write data.
 14. The data storage control apparatusaccording to claim 13, wherein said writing controller waits for Ybanks' worth of said write data to be accumulated in said output buffermemory, where Y is an integer of 2 or more, and collectively writes saidY banks' worth of said write data to said memory.
 15. The data storagecontrol apparatus according to claim 11, wherein upstream of said inputbuffer memory, image processing is performed in units of microblocks,and a predetermined number V of said second blocks corresponds to apredetermined number W of said microblocks, where V and W are integersof 1 or more.
 16. A data storage control apparatus comprising: acompressor that compresses image data and outputs compressed data; awriting controller that writes said compressed data as write data in amemory; and an input buffer memory that temporarily stores said imagedata that is to be supplied to said compressor, wherein said compressorcompresses said image data in units of first blocks, each being an imageblock of a predetermined area size, and outputs said compressed data inunits of second blocks, each including a predetermined number N of saidfirst blocks, where N is an integer of 1 or more, processing performedby said compressor includes reference-type processing that uses, as areference object, a first block that is not set to a compression objectamong said first blocks, and said input buffer memory stores said imagedata of a first block that is scheduled to be used as either saidcompression object or said reference object, and frees a storage areaallocated to a first block that is no longer scheduled to be used aseither said compression object or said reference object, at apredetermined timing.
 17. The data storage control apparatus accordingto claim 16, wherein said compressor acquires said image data in unitsof third blocks, each including a predetermined number X of said secondblocks, where X is an integer of 1 or more, from said input buffermemory, and said input buffer memory manages said storage area inassociation with said third blocks.
 18. The data storage controlapparatus according to claim 16, further comprising: an output buffermemory that temporarily stores said write data that is output from saidcompressor for the supply to said writing controller, wherein saidmemory includes a plurality of banks, and said writing controller writessaid write data to said memory while switching said plurality of banksevery piece of said write data.
 19. The data storage control apparatusaccording to claim 18, wherein said writing controller waits for Ybanks' worth of said write data to be accumulated in said output buffermemory, where Y is an integer of 2 or more, and collectively writes saidY banks' worth of said write data to said memory.
 20. The data storagecontrol apparatus according to claim 16, wherein upstream of said inputbuffer memory, image processing is performed in units of macroblocks,and a predetermined number V of said second blocks corresponds to apredetermined number W of said microblocks, where V and W are integersof 1 or more.
 21. A data storage control method comprising: (a)compressing image data and outputting compressed data; (b) writing saidcompressed data as write data to a memory; and (c) temporarily storingsaid image data used in said step (a) in an input buffer memory, whereinsaid step (a) includes compressing said image data in units of firstblocks, each being an image block of a predetermined area size, andoutputting said compressed data in units of second blocks, eachincluding a predetermined number N of said first blocks, where N is aninteger of 1 or more, said step (a) includes reference-type processingthat uses, as a reference object, a first block that is not set to acompression object among said first blocks, and said step (c) includesstoring said image data of a first block that is scheduled to be used aseither said compression object or said reference object in said inputbuffer memory, and freeing a storage area of said input buffer memorythat is allocated to a first block that is no longer scheduled to beused as either said compression object or said reference object, at apredetermined timing.